A DAC having a segmented structure typically operates by dividing a digital input word into subwords which control different parts of the DAC circuit. For example, a digital input word might be divided into a more significant (MS) subword and a less significant (LS) subword, the MS subword being used to generate a first intermediate current or voltage signal that is summed with a second intermediate voltage or current signal generated responsive to the LS subword. Such segmented architectures are particularly useful for reducing the number of resistive elements required to provide a resistive DAC with high resolution. However, summing the intermediate signals without buffering the outputs of the signal generating circuits may subject the outputs of the signal generating circuits to excessive load conditions. On the other hand, adding such buffering to the output of each signal generating circuit typically introduces noise and adds to the cost and complexity of the DAC.
U.S. Pat. No. 6,225,929 describes a DAC architecture which switches currents to binary weighted resistors. This architecture is specifically adapted to tackle the problems associated with buffering highlighted above. The static DAC design of this US patent is adapted for converting an N bit input digital word to a corresponding analog output. This is achieved by providing a resistor string having N resistors and coupling each of N switchable current sources to a corresponding one of N nodes of the resistor string. This DAC is useful for high resolution general purpose applications but suffers in that it is not suitable in applications that require monotonic behaviour.
This problem of monotonicity arises from the transfer function of the DAC. Monotonicity is vital in many applications such as in control systems where non-monotonic DACs can create serious problem. In many practical cases, however, due to unavoidable component inaccuracies in the DACs, monotonicity is not always guaranteed.
In view of the foregoing, it is desirable to provide a segmented DAC which is simple to implement, and which provides immunity to loading problems associated with unbuffered analog summing of intermediate signals. It would further be desirable to provide a segmented DAC which does not require a separate buffer circuit between the output of each signal generating circuit and the summing circuitry of the DAC. It would also be desirable to provide monotonic transfer function of the DAC.